The present invention relates to serializer-deserializer (SERDES) circuits, which are known in the art. More particularly, the present invention relates to an improved SERDES circuit that provides stable, error-free operation in the presence of a non-ideal operational environment in a short period of time.
A serializer-deserializer (SERDES) is a negative feedback loop where an input phase of a clock-data recovery (CDR) block can be automatically synchronized (“locked”) to the phase of a periodic input signal. The periodic input signal is commonly referred to as the recovered clock. The data tracking property of the SERDES has numerous applications in telecommunications; for example, Synchronous Optical Networks (SONET), data communications, storage technology such as Serial Attached Small Computer System Interface (SCSI) (SAS) and Serial Advanced Technology Attachment (SATA) computer storage systems, memory technology such as Dynamic Random Access Memories (DRAM) serial interfaces, and any other serial data transfer application. A basic SERDES has four components connected in a feedback loop: a CDR block, a loop filter, which is generally some implementation of a Low-Pass Filter (LPF), a Control (CTRL) block, and a phase adjustment block. Additionally, a basic SERDES includes some type of data demultiplexing to convert the higher speed serial data stream into a lower speed parallel data stream.
The CDR block is a phase detector whose function is to sample the data stream at zero-degrees (called the “transition sample”) and 180-degrees (called the “data sample”) and determine whether the transition sample does not match the data sample on the leading (zero-degree) sample or the trailing (360-degree) sample when there is a data transition. The sample mismatch, transition-data (TD) or data-transition (DT), detects the presence of a phase offset from the ideal locked condition. If the mismatch is TD, the data sample is skewed earlier than the ideal 180-degree position. If the mismatch is DT, the data sample is skewed later than the ideal 180-degree position.
The output of the CDR block is the sample state, TD or DT, and is used by the CTRL block to shift the operating point of the recovered clock to the in phase condition with the input data. The LPF integrates the input TD and DT pulse train and creates a lower rate output pulse train suitable for lower speed control logic. These filtered pulse trains are input to the CTRL block wherein state machines produce the phase adjust signals and determine the operating point for the phase adjust cycle. The output of the control block feeds a phase selection block which controls the phase of the recovered clock. This closes the loop for the SERDES macro and provides the negative feedback required for stable operation.
For a SERDES to lock the phase of the recovered clock to the data stream quickly, the control block needs to provide a fast adjustment rate to converge on the proper phase alignment in a minimum number of data bits. The longer the recovered clock takes to lock to the proper phase, the more data bits are lost due to the CDR block being at an incorrect sample point. To facilitate rapid convergence, a multi-rate convergence algorithm may be used to provide coarse adjustments for preliminary alignment followed by finer adjustments to complete the phase adjustment of the recovered clock to be aligned with the data stream.
The rapid convergence enables a practical implementation of a group of four such SERDES circuits, initially at zero-degree, 90-degree, 180-degree, and 270-degree sample locations, to recover any data stream without loss. The fast convergence enables small data buffers to hold the data stream until the proper error free stream can be determined. Once this data stream is detected, all data emerging from the data buffers will be error free from the initial data sample. The depth of the data buffers is less than N-bits, where N is defined as two times the number of phases in a single data bit. This quad-redundant SERDES architecture would also provide single-event upset (SEW immunity in the presence of ionizing radiation such as encountered in space applications.
Jitter tolerance is also a primary requirement for a SERDES implementation. Jitter types can cause periodically shifting transition positions (sinusoidal jitter), or a random movement of the data transition (random jitter), or the compression or expansion of the bit width due to data distortions introduced by the electronic circuitry in the data path (deterministic jitter). A SERDES must tolerate a specific amount of jitter comprised of all types to be acceptable for a particular application. One conventional approach to damping the jitter response is to require a large number of data transitions to filter jitter induced phase adjustments. This approach provides a very stable control loop but a very long lock time to align the recovered clock with the data. Alternatively, a filter may be employed to reduce the effects of jitter on the positioning of the recovered clock while allowing for a faster lock time.
Error conditions must also be accounted for in a SERDES architecture. A primary error state is a 180-degree out of phase condition being detected as “locked” by the control block when a non-ideal data stream is input. Numerous approaches have been used to eliminate this error from a SERDES implementation. Another error state is the stability and response of the SERDES to a mismatch between the data rate and the recovered clock. This data and clock frequency offset is a specification of SERDES end uses, ranging from 200 parts-per-million (ppm) to over 5000 ppm. The greater the frequency mismatch between the data and the recovered clock, the more attention stability issues must receive for proper operation in the presence of jitter.
Implementations of SERDES designs range from analog control loops built around a Phase Locked Loop (PLL) phase detector which are very stable but have a very slow response time, to all digital approaches, which can have fast response times but can be more susceptible to noise effects. The primary requirement of any SERDES is a phase detector to monitor the phase relationship between the data stream and the recovered clock. Once the phase error is detected, the clock and data must have a mechanism to enable aligning one with the other.
As is described further in the “Detailed Description” section below, a SERDES design must provide stable, error-free operation in the presence of a non-ideal operational environment.